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Making Chips Beyond 14nm

One of the big things at this week's International Solid States Circuits Conference (ISSCC) was a discussion of how the industry will create processors at 10nm and below, and whether doing so will be cost effective.

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One of the big things at this week's International Solid States Circuits Conference (ISSCC) was a discussion of how the industry will create processors at 10nm and below, and whether doing so will be cost effective.

Intel Senior Fellow Mark Bohr gave a highly covered talk on a panel where he reiterated Intel's belief that Moore's Law – the concept that chip density can double in each succeeding generation – is continuing. As Intel has said before, Bohr said he believes it can manufacture chips at 10nm and even 7nm using existing lithography tools, though it would certainly like to have extreme ultraviolet (EUV) lithography tools ready to go for 7nm.

Intel Integrated Systems – slide 7Intel Integrated Systems – slide 7Intel Integrated Systems – slide 7

His big point was that continuing scaling always has required new innovations in processes and design (such as the introduction of copper connections, strained silicon, high-K/metal gate, and FinFET technology), and that further innovation will be necessary to continue the scaling to 10 and 7nm and below. But he did not give any new details as to what changes to process, materials, or structures Intel will be using on the new nodes.

Contrary to some published reports, Bohr did not actually confirm that Intel will be shipping 10nm parts in 2016. (Given that Intel shipped its first 14nm chips at the end of 2014, shipping 10nm next year would match the typical two-year cadence of process nodes; when I asked Intel CEO Brian Krzanich whether the two-year cadence will continue, he said that Intel believed it could.) Intel's 14nm process ramped slower than expected, and while Bohr said its 10nm pilot line is showing a 50 percent improvement in throughput compared to where 14nm was at the same point in its progress, the company doesn't want to make a firm commitment.

Bohr was clear that he expected that not only will chip scaling continue, but that while the cost of making each wafer will continue to rise, increasing density of transistors will be enough so that Intel's manufacturing cost per transistor will continue to decline enough to make it worthwhile to continue scaling. He's said this before, but it contrasts with some other companies that have been more skeptical.

Intel – Moores Law Challenges – slide 5Intel – Moore's Law Challenges – slide 5

He pointed out that the history of chip design includes more and more integration, with modern System-on-Chip (SoC) designs now integrating things such as different levels of power, analog components, and high-voltage input-output systems. The future may lend itself to 2.5D chips (where separate dies are connected through an internal bus on the package) or even 3D chips (where through-silicon vias or TSVs connect multiple chip dies.) He said such systems will be good for system integration, but poor for low cost.

Bohr said 3D chips with TSVs don't really work for high-performance CPUs because you can't get sufficient TSV density or deal with the thermal issues, and that even on mobile SoCs, where it is technically more feasible, it hasn't really been used yet because it adds too much cost.

Other vendors had different perspectives, as you might expect.

Samsung – Transistor Scaling – slide 8Samsung – Transistor Scaling – slide 8

Kinam Kim, president of Samsung Electronics pointed out that density – the number of transistors per chip area – has continued to increase.

Samsung – Theoretical Limit – slide 9Samsung – Theoretical Limit – slide 9

But he also pointed out that we are approaching a theoretical limit at 1.5nm, and that with EUV combined with quadruple pattern printing, it is theoretically possible to get to 3.25nm. But he expected that to get there, the industry will need new tools, structures, and materials.

Samsung – Future of Logic CMOS – slide 12Samsung – Future of Logic CMOS – slide 12

For instance, he suggested Samsung might move its logic production from FinFETs (which Intel started producing a few years ago, and Samsung just started shipping) to gate-all-around and Nanowire contacts around 7nm, followed by tunnel FETs. At that point, the company is considering new materials as well. He noted that DRAM and NAND technology already includes many new features, including 3D manufacturing.

While leading foundry TSMC didn't give a specific technology presentation, it too is working on new materials and structures as it readies development of its 16nm manufacturing this year, and future nodes to come.

I was particularly interested in a somewhat different view of where the industry was heading given by Sehat Sutardja, CEO of Marvell Technology Group.

He complained that the cost of creating a "mask" (the template for creating a chip) was more than doubling each generation, and that at current rates, it could get up to $10 million by 2018. As a result of these mask costs and R&D, he said, making an SoC on the current FinFET technology only makes sense if the total lifetime volume of the chip will be very large – 25 million units or more. Yet the market is so fragmented, it is hard for most companies to have a large enough volume.

Marvell – Too much integration – slide 6Marvell – Too much integration – slide 6

Sutardja said that current mobile SoCs have "too much integration for our own good," noting how many of the features that are integrated into a mobile chip (such as the Southbridge for I/O connections, connectivity options for Wi-Fi and Bluetooth, and the modem) are still not integrated into desktop and laptop processors.

Marvell – MoChi Configuration – slide 13Marvell – MoChi Configuration – slide 13

Instead, he proposed the industry move to what he called MoChi (for Modular Chip), which will involve a Lego-like concept of plugging together individual components into a "virtual SoC." This, he said, will allow a separation of compute and non-compute function, with the CPU and GPU functions produced on the most advanced nodes, and other functions at different, less expensive nodes. These components will be connected via an interconnect that will be an extension of the AXI bus. It's an interesting idea, particularly for the smaller vendors, though a lot of companies will probably need to get on board to make this a viable standard.

Getting to newer and better chips has never been easy, but it seems harder now than it has been, and certainly more expensive. The result could be fewer competitors and longer time between nodes, but it still appears that chip scaling will continue.

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About Michael J. Miller

Former Editor in Chief

Michael J. Miller is chief information officer at Ziff Brothers Investments, a private investment firm. From 1991 to 2005, Miller was editor-in-chief of PC Magazine,responsible for the editorial direction, quality, and presentation of the world's largest computer publication. No investment advice is offered in this column. All duties are disclaimed. Miller works separately for a private investment firm which may at any time invest in companies whose products are discussed, and no disclosure of securities transactions will be made.

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