The companies that make processors have a long-held obsession with getting smaller. The famous—and increasingly obsolete—Moore’s Law dictated the regular shrinking of chips for decades. But what happens when downsizing no longer does the trick like it once did? Rather than simply narrowing in, Intel has found a way to build up.
On Wednesday, the chip giant demonstrated its new 3-D packaging technology, called Foveros, which allows it to stack logic chips atop one another. Various methods of going vertical have boosted memory chips recently, but after years of research, Intel will be the first to bring 3-D stacking to CPU, graphics, and AI processors at scale. It’s not exactly what Gordon Moore had in mind—but it may prove even better.
The significance of stacking extends beyond simply saving space, although that’s certainly a big part of it. It also allows you to customize combinations of silicon to your specific needs.
“You can pack more transistors in a given space,” says Raja Koduri, Intel’s chief architect. “And also you can pack different kinds of transistors; if you want to put a 5G radio right on top of a CPU, solving the stacking problem would be great, because you have all of your functionality but also a small form factor.”
The rest of the industry has already glommed onto the benefits of mixing and matching transistors, investing in “chiplets” that can be used almost like microscopic interlocking puzzle pieces. That all still happens on a flat plane though; think of Intel’s 3-D stacking technology as more of a Lego brick solution.
“It’s changing the concept of the architecture,” says Maribel Lopez, founder of Lopez Research, a technology research firm.
That change comes with practical benefits. The 2-D approach allows for some variety, but also sacrifices performance and draws more power, says Patrick Moorhead, CEO of Moor Insights & Strategy. Intel appears to have dodged those issues. “What is so astonishing about what has been presented is there’s virtually no power loss and no performance loss when you’re putting these chiplets together,” says Moorhead, who cautions that Intel still needs to prove that it can produce the same results across millions of chips, versus a single demonstration.
Power delivery, too, turns out to be just one problem that Intel believes it has solved. A successful 3-D packaging technology has been sought after for decades, but has been tripped up by power, heat, and price. “If the bottom layer gets hot, the heat goes up,” says Koduri. “And in the 3-D stacking approach, if you realize after you’ve assembled everything that one of the layers of the stack is bad silicon, you throw away everything. That’s very, very expensive.”
Koduri keeps the specifics of exactly how Intel cracked those problems closely held. But he says that a combination of rigorous testing, a new power delivery process, and a wholly invented insulation material to dissipate the heat has helped the company avoid the typical pitfalls.
On one level, Intel has just solved a bedeviling physics problem. That’s interesting enough in its own right. But as a breakthrough, it matters even more for the types of experiences it will help enable.
“There’s still this interesting physics challenge that’s happening around things that are smaller or newer form factors,” says Lopez. “It helps with those complex form factors, like foldable, bendable, lightweight things.”
Which, as a reminder, are coming sooner than you might think. Intel says consumer products with Foveros inside will start shipping within the next 12 to 18 months. By then, Samsung will likely have already shipped its first foldable smartphone.
But the even more interesting advantages may prove more subtle. Because the new architecture allows manufacturers to swap in whatever transistors best suit their needs, countless devices could become much more efficient by virtue of the stack.
“The transistor that’s best for a desktop gaming CPU is not necessarily the best transistor for a GPU. Similarly, you need different transistors for running 5G and interconnectivity,” says Koduri. Artificial intelligence has still different needs, and so on. “Before, we used to just take the best compromise of all of the silicon. Now, we can take processes that are best for the function and put them all together on a single package. And because we have very high bandwidth between these chips, they will function exactly as if they are a single chip.”
That customizability should help Intel in the long run, too. Even in the server space in which it dominates, it faces increasing competition from companies like Google and Amazon, who have of late opted to create their own chips in-house. Now, Intel can offer them something unique, creating a potential avenue to work with them rather than against. “There’s no reason that Facebook or Google or AWS couldn’t put their own custom, proprietary chiplet into an Intel design,” says Moorhead.
The caveats that accompany any new technology apply here as well. Intel says it can scale Foveros, but still has to actually do it. And device manufacturers and other partners need to get onboard as well. Intel did, after all, miss out on practically the entire mobile generation, and faces stiff competition from companies like AMD, Qualcomm, and TSMC, some of whom have already made the leap to processors made on a 7nm process, while Intel lingers on 10nm.
But ultimately, what the new 3-D stacking proposes is that the race to get small no longer matters in the way it once did, replaced instead by a pursuit of tall. Intel introduced a handful of other iterative advances Wednesday, including its new Sunny Cove CPU microarchitecture and Gen11 integrated graphics. But the 3-D packaging proposes something that’s instead transformative: a new way to think about how chips are built, and a new engine to keep Moore’s Law humming.
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