IBM Discloses Future POWER Roadmap At OpenPOWER Summit With Support From Google And Rackspace

At the recent OpenPOWER Summit I attended in San Jose, IBM disclosed important updates to the POWER roadmap that give more insight into the company’s architectural decisions. IBM’s partners also made many overall POWER announcements which I wrote about here. IBM’s POWER architecture, which is now part of the OpenPOWER Foundation, has been a popular architecture for compute intensive applications like high performance computing (HPC). The new roadmap announced at the OpenPOWER Summit updates the features that have made the POWER architecture attractive to those in the high performance computing world. They have enhanced the threads, throughput, acceleration and coherency. In addition to the improvements, IBM also had big names put their support behind the new architecture, validating their design decisions.

POWER shifts to lower cost and more acceleration

The big announcements that IBM made around the POWER architecture were primarily around the POWER9 processor and surrounding architecture. IBM Fellow and VP of POWER Development Brad McCredie talked through the entire POWER processor roadmap detailing the major improvements of the POWER9 architecture over the previous generations of POWER, including POWER8 and POWER8 with NVLink+.

McCredie talked about how IBM’s focus on the POWER8 and POWER9 architectures towards lower cost and more acceleration. This doesn't mean performance and technology aren't important, they are, but new generations should cost less and accelerate more. For 2016, we can expect to see POWER8 chips with built-in NVLink interconnects with up to 24 cores and an enhanced micro-architecture all built on 22nm. However, 2017 is when we can start to see the benefits of FinFET with the POWER9 architecture.

The new POWER9 architecture brings a whole host of major improvements starting with an entirely new architecture. The new POWER9 SO (Scale Out) chip will be the first in the family of POWER9 processors from IBM and will have 24 POWER9 cores, which is double the previous generation’s core count. Unlike mobile applications, server workloads can benefit from more cores via virtualized and containerized workloads.

This new processor will also leverage what IBM calls “execution slices” for improved performance on analytics, big data crunching and cognitive computing. The POWER9 SO will also have a large, low-latency eDRAM cache in order to accommodate larger datasets easily. For actual system memory, the POWER9 architecture calls for DDR4 support with direct attach memory channels. All of this is nicely fit onto a 14nm chip manufactured with the eDRAM by Globalfoundries using their 14HP (14nm High Performance) FinFET process. The HP process is a very different, higher performance-higher leakage process than used in mobile SoCs.

POWER9 the I/O beast

In terms of I/O, the POWER9 SO is not short on any kinds of connectivity with both PCIe Gen 4 and NVLINK 2.0 for high-bandwidth GPU interconnections. There will also be an updated CAPI 2.0 interface for coherent accelerators and storage attachments. The new 25 Gbps advanced accelerator attach bus will primarily be what powers the Nvidia NVLink 2.0 and other IBM & partner devices. Based on IBM’s own diagrams, it also appears that IBM will include a 16 Gbps interconnect between POWER9 processors. This lends to IBM’s vision for POWER9 being optimized for 2-socket scale out servers and hyperscale datacenters.

Google and Rackspace build POWER9 server

In addition to these POWER9 announcements, Google and Rackspace both announced that they are already developing POWER9 servers. Google announced that it is developing a server based on the Open Compute Project form factor with OpenPOWER inside, more specifically POWER9. Google is working with Rackspace to co-develop the open server specification based on the POWER9 architecture and the two companies will submit a potential server design to the Open Compute Project in an unspecified timeframe.

We already know the first POWER9 customers

While Google and Rackspace may not be real customers quite yet, IBM already has some major customers for POWER9, well technically one customer with multiple installations. I am of course talking about the US Government and the Summit and Sierra Supercomputers that IBM, Nvidia and Mellanox jointly won together. All three companies are founding members of the OpenPOWER Foundation and their relationships with each other as a result of the OpenPOWER Foundation are what really allowed IBM, Nvidia and Mellanox to win the $325 million government tender which utilizes POWER9 as the core processor architecture.

This government tender is a part of the CORAL (Collaboration of Oak Ridge, Argonne and Lawrence Livermore) initiative from the U.S. Department of Energy which awarded $525 million to build state of the art supercomputers. $325 million of the total is going towards building the Summit supercomputer at Oak Ridge National Laboratory and Sierra at Lawrence Livermore National Laboratory. The goal of this initiative was to streamline the procurement process and improve the ability of the systems to share information and communicate amongst each other and to deliver over 100 PetaFLOPS of performance.

Wrapping up

The POWER roadmap announced at the OpenPOWER Summit was fairly expected by most, as many of the things that IBM has been talking about have been inferred from many of their supercomputer design wins as well as other technology announcements. Many of these improvements and announcements are expected and more of the same in terms of improvements to the flexibility and scale-out. We could actually see a strong Intel reaction to IBM’s announcements with POWER9, especially with improving the accessibility to their QPI interface. It isn’t that Intel doesn’t have the technology, they do, they’re simply more focused on high volume opportunities. The challenge for Intel becomes if POWER9 becomes a volume player in the big data and analytics space and starts to encroach upon Intel’s growth segments with Xeon E7.